Semiconductor device geometries (i.e., integrated circuit design rules) have decreased dramatically in size since integrated circuit (IC) devices were first introduced several decades ago. ICs have generally followed “Moore's Law,” which means that the number of devices fabricated on a single integrated circuit chip doubles every two years. Today's IC fabrication facilities are routinely producing 65 nm (0.065 μm) feature size devices, and future fabs will soon be producing devices having even smaller feature sizes.
As IC design rules shrink, an increasing trend in semiconductor manufacturing is utilizing single-wafer processing for a variety of fabrication steps, including plasma etching and deposition chambers. Single-wafer reactors must be designed to unobtrusively secure the wafer (or other substrate-type) during processing, while controlling both temperature and temperature uniformity across the wafer.
Mechanical wafer clamps which engage a portion of front surfaces of the wafer where processing is to be performed potentially create process uniformity problems by interfering with gas flow, altering plasma distribution, and acting as a heat sink. If improperly designed, mechanical wafer clamps may also produce particulates with resulting contamination of the wafer as well as other problems.
An electrostatic chuck (ESC) uses an electrostatic potential to hold a wafer in place during processing, thus avoiding the problems of mechanical clamping by having contact with only the back side of the wafer. Electrostatic chucks operate by inducing opposing charges on the substrate and the chuck thereby resulting in an electrostatic attraction between the chuck and the substrate. A degree of attraction is dependent on an amount of charge induced as well as a rate at which the charge dissipates due to conductive effects. Voltage biasing is employed to induce and control the electrostatic force and may be applied for only a portion of a processing cycle, for example, just after a substrate is transferred to the chuck. Alternatively, voltage biasing may be applied continuously throughout a processing cycle. For instance, using the conduction properties of plasma can provide a means of electrical connection to one terminal of a ESC and wafer system.
With reference to FIG. 1, a portion of an exemplary prior art ESC structure 100 includes an anodized aluminum base 101, a heater bond layer 103, a heater 105, a heater plate 107, and a ceramic bond layer 109. The ESC structure 100 is capped with a ceramic top piece 111. The heater bond layer 103, heater 105, heater plate 107, and ceramic bond layer 109 are protected from direct contact with a surrounding plasma environment and caustic chemicals by an edge bonding seal 113.
The heater bond layer 103 is typically comprised of a silicone layer impregnated with silica (e.g., amorphous SiOx). The heater 105 is frequently comprised of metallic resistance elements encapsulated in a polyimide while the heater plate 107 is typically fabricated from aluminum. A ceramic-filled (e.g., alumina (Al2O3)) silicone material is commonly employed for the ceramic bond layer 109. The ceramic top piece 111 is commonly fabricated from alumina.
The edge bonding seal 113 may be comprised of, for example, epoxy, silicone, or polyimide based polymers. The edge bonding seal 113 protects the heater 105, the heater plate 107, and the heater 103 and ceramic 109 bonding layers from plasma erosion. However, the edge bonding seal 113, as noted above, is exposed to the plasma and erosion from both chemical reactions and ion bombardment can occur. In addition to the erosion effects, damage caused by factors such as fracturing or delamination may be caused by fast temperature ramps or differences in material coefficients of thermal expansion, since the ESC structure 100 operates over a wide range of temperatures.
Further, direct exposure of bond lines to plasma can result in particle generation, potentially having a deleterious effect on device yields. Erosion of the bond lines prevents future edge bead refurbishment and impacts ultimate part lifetime. Therefore, an indicator mechanism is needed to limit maximum edge bead erosion depths and minimize wafer yield impacts and decrease total tool operating costs.